Programming a NAND-type flash EEPROM device is operable with the repetitive cycles of programming, data read-out, and program verifying, and Y-SCAN. Specifically, during the program cycle, EEPROM cells associated with a selected page (i.e., a word line) are programmed into a desired data state. The data read-out operation of the programmed cells is then performed. Finally, the verifying operation is carried out in order to check whether the programmed cells are situated in the desired data state. If at least one of the programmed cells does not correspond to the desired state, the above program cycles are continuously performed for predetermined times. To this end, most of flash memory devices include a program status detection circuit to determine PASS or FAIL, informing of a result of the programming.
A program status detection circuit for flash memories, for example, is disclosed in U.S. Pat. No. 5,299,162, entitled "NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND AN OPTIMIZING PRGRAMMING METHOD THEREOF".
FIG. 1 illustrates the program status detection circuitry disclosed in the above-mentioned document. Referring now to FIG. 1, each of bitlines BL1-BL1024 is coupled to a NAND-structured cell string (CE) composed of a serial-connected transistor ST, eight cell transistors CT1-CT8, and a ground selection transistor GT. The string selection transistor ST and the ground selection transistor GT have a MOS transistor structure. Gates are coupled to selection lines SL1 and SL2, respectively. Each of the cell transistors CT1-CT8 has a structure of a depletion MOS transistor having a floating gate placed between a control gate and a substrate. Each control gate is coupled to each of the control lines CL1-CL8. Each of the bitlines (BL1-BL1024) is coupled to each of high voltage supply circuits HV for supplying program voltage with positively high level, each of bitline latch circuits LT on which externally inputted data is loaded, a current source circuit CS for supplying detection current during program detection operation, and each of program check units PC for inverting data of the bitline latch circuit LT.
The high voltage supply circuit HV is a charge pump circuit composed of transistors PT1 and PT2 and a pumping capacitor C1. A drain of the transistor PT1 is coupled to program voltage Vpp, a gate thereof is coupled to a bitline BL1, and a source thereof is coupled to a gate of a transistor PT2. A drain of the transistor PT2 is coupled to one electrode of a pumping capacitor C, and a source thereof is coupled to the bitline BL1. When a clock signal .O slashed.pp goes to high level, the pumping capacitor C discharges charge stored in a capacitor C to the bitline BL1 through the transistor PT2 and supplies erase voltage and program inhibit voltage to the bitline.
The bitline latch circuit LT is formed of two inverters INV1 and INV2, and a transfer transistor TT1. The inverters INV1 and INV2 are coupled to each other, coupling an input of one of them to an output of the other. A gate of the transfer transistor TT1 is coupled to a clock signal .O slashed.1, a first current terminal (drain or source) thereof is coupled to a bitline, and a second terminal thereof (source or drain) is coupled to an input of the inverter INV2. Thus, the bitline latch circuit LT receives and holds external data applied to the bitline through the transfer transistor TT1 being turned on when the clock signal .O slashed.1 is on high potential.
The current source circuit CS includes a plurality of output circuits OS coupled to each of bitlines and a common reference current setting circuit RC. The circuits RC and OS are coupled to each other in the form of a current mirror circuit so as to establish reference current against all the output circuits OS. The common reference current setting circuit RC comprises a P-channel MOS transistor M1, coupled between power supply voltage Vcc and ground voltage Vss, and N-channel MOS transistors M2 and M3. A drain and a gate of the P-channel MOS transistor M1 are coupled to each other. A gate of the N-channel MOS transistor M2 is coupled to reference voltage Vref, and that of the N-channel MOS transistor M3 is coupled to a clock signal .O slashed.2. Each of the output circuits OS has a P-channel MOS transistor M4, coupled between the power supply voltage Vcc and each of the bitlines, and an N-channel MOS transistor M5. A gate of the P-channel MOS transistor is coupled to that of the P-channel MOS transistor. A gate of the N-channel MOS transistor M5 is coupled to the clock signal .O slashed.2. Thus, the current source circuit CS is enabled when the clock signal .O slashed.2 goes to a high level, so that drain current of the P-channel MOS transistor M4, i.e., verifying current, is supplied to the bitline BL1.
The program check circuit PC includes a MOS transistor M6. A drain of the MOS transistor M6 is coupled to an input of the inverter INV1, a source thereof is coupled to the ground voltage Vss, and a gate thereof is coupled to a bitline. If the verifying current applied to the bitline dose not flow to a ground through a NAND-structured cell string including a selected cell, the bitline goes to high level and consequently the MOS transistor M6 (program verifying unit) is turned on. This makes the input of the inverter INV1 go to low level (e.g., ground voltage). Thus, when programming the selected cell is insufficient, the program check circuit PC detects an insufficient programming state and then invert a data logic level of the bitline latch circuit LT.
In FIG. 1, there is program status detection circuit PS. When all the selected cells are programmed with an optimal state, the circuit PS outputs a normal detection signal. When at least one of the selected cells is insufficiently programmed, the circuit PS outputs an abnormal detection signal. The circuit PS includes a P-channel MOS transistor M7 and a depletion MOS transistor M8. The P-channel MOS transistor M7 serves as a pull-up circuit for pulling up a node N1, and the depletion MOS transistor M8 serves as a pull-up load. A source of the P-channel MOS transistor is coupled to the power supply voltage Vcc, a gate thereof is coupled to a clock signal .O slashed.3, and a drain thereof is coupled to a source of the depletion MOS transistor M8. A gate and a drain of the depletion MOS transistor M8 are coupled to the node N1. A plurality of N-channel MOS transistors PD1-D1024, serving as a pull-down circuit PD, are coupled between the node N1 and a ground voltage Vss in parallel. A gate of each of the MOS transistors is coupled to an inverted output Q of the bitline latch circuits LT. The node N1 is coupled to one input terminal of a NOR-type gate G through an inverter INV3. The other of the NOR-type gate G is coupled to a clock signal .O slashed.4.
Program and verifying operations of the nonvolatile semiconductor memory device shown in FIG. 1 will be described more fully hereinafter.
First, an erase operation for making a threshold voltage of a cell into a negative level is performed before programming data into a cell. After completion of the erase operation, external data is loaded on the bitline latch circuit LT. At this time, logic high level is loaded to data "1" and logic low level is loaded to data "0". When the clock signal .O slashed.1 is at high level, the data is loaded on the bitline latch circuit LT. If the data held thereon is at high level, the high voltage supply circuit LT is operated to set a voltage on a bitline as a program inhibit voltage. Because voltage difference between a gate and a drain of a selected cell transistor (e.g., CT6) is insufficient for generation of F-N tunneling, the selected cell transistor CT6 has a negative threshold voltage.
When the data loaded on the bitline latch circuit LT is at low level, the high voltage supply circuit HV is not operated and retains 0V on the bitline. Accordingly, because the F-N tunneling is generated by the voltage difference therebetween, charges are injected into a floating gate and consequently the cell threshold voltage goes to a positive level. However, insufficient programming prevents the selected cell transistor from obtaining the set positive threshold voltage. To check whether cells are correctly programmed after completion of the program operation, the current source CS is operated in response to a high status of the clock signal .O slashed.2 and consequently verifying current is supplied to the bitline BL. The control lines CL1-CL5, CL7, and CL8 receive the power supply voltage Vcc and the control line CL6 receives a predetermined verifying voltage (e.g., +0.8V). When the threshold voltage of the selected cell transistor CT6 goes to a negative level, the verifying current flows to the ground through the cell string CE. Thus, the bitline BL1 retains 0V.
When the threshold voltage of the selected cell goes to a positive level (Vth&gt;0.8V), the bitline BL1 goes to a high level because the verifying current dose not flow through the cell string CE. When the selected cell is insufficiently programmed (it means that the threshold voltage thereof is lower than 0.8V), the verifying current flows to the ground and the bitline BL1 still retains OV.
During program verifying operation, the transistor M6 for checking a program is turned off when the bitline of the selected cell is laid on a low level. As a result, data stored in the bitline latch circuit LT is not inverted to make data "0" of an initially loaded state be held on an output Q. Since data "1" is held on an inverted version Q of the output Q, the pull-down transistor PD1 of the program status detection circuitry PS coupled to the version Q is continuously turned on. Therefore, the program is abnormally performed to make a clock signal .O slashed.5 of the program status detection circuitry PS retain a low level.
During reprogram operation, the data "0" of the bitline latch circuit LT is supplied to the bitline BL1 within a high interval of the clock signal .O slashed.1 again. Charges are repeatedly injected into the floating gate of the insufficiently programmed cell, so that the threshold voltage of the cell has a higher positive voltage. If the program cycles are sequentially carried out to charge up the threshold voltage of the selected cell having the higher positive voltage and consequently the selected cell is not turned on by the verifying voltage (0.8V), the bitline goes to a high level to turn on the transistor M6. Thus, the data "0" loaded on the output Q of the bitline latch circuit LT is inverted to data "1" and data "1" of the inverted version Q is inverted to data "0". So the pull-down transistors PD1 of the program status detection circuitry PS is turned off. By these repeated operations, complementary outputs Q of all the bits (i.e., all the bit line latch circuits) of the page buffer PB go to data "0". When the all the complementary outputs Q go to a low level, the clock signal .O slashed.5 of the program status detection circuitry PS goes to a high level. That is, all the selected cells are programmed with a required status.
As known by the above description, a nonvolatile semiconductor memory device having a program status detection circuitry shown in FIG. 1 can simultaneously verify a program status of cell transistors related to one page. However, a conventional nonvolatile semiconductor memory device is regarded as a fail device and causes deterioration of a yield. Hereinafter, this will be described in detail.
Referring now to FIG. 2, when two adjacent bitline latch circuits LT1 and LT2 are electrically connected to each other as indicated by a dotted line, as apparent to those skilled in the art, bit lines BL1 and BL2 coupled to the circuits LT1 and LT2 substitute for redundant bitlines (not shown) supplied to a cell array. However, because complementary outputs Q of the bitline latch circuits LT1 and LT2 always have logic states being contrary to each other, one of the pull-down transistors PD1 and PD2 coupled to the complementary outputs Q is always turned on during the program verifying operation. For example, if the bitline BL1 or BL2 is set to a low level, the bitline BL2 or BL1 electrically connected thereto is also set to the low level. As a result, the complementary output Q of the bitline latch circuit LT1 goes to a high level, as shown in FIG. 2. This makes the pull-down transistor PD1 coupled to the complementary output Q turned on, so that the program status detection circuitry PS outputs low-leveled clock signal .O slashed.5 indicating program fail until a series of the program operation and the program verifying operation are repeated as many as predetermined times. That is, the nonvolatile semiconductor memory device is regarded as a fail device.
If any bitline is coupled to a ground voltage (it is regarded as a defective column to substitute for a redundant bitline), a complementary output Q of a bitline latch circuit coupled to a grounded bitline always retains a high level. Consequently, a program state detection circuitry PS outputs a low-leveled click signal .O slashed.5 indicating program fail. If a cell transistor, which will be programmed, is continuously at an erase state (a bitline coupled to a cell string having the cell transistor of the erase state substitutes for a corresponding redundant bitline), the complementary output Q always retains a high level. Consequently, the program status detection circuitry PS outputs the low-leveled clock signal .O slashed.5.
As mentioned above, although defective bitlines substitute for redundant bitlines, a conventional program status detection circuitry always outputs a low-leveled clock signal indicating program fail owing to the defective bitlines. Therefore, a nonvolatile semiconductor memory device is regarded as a fail device and causes deterioration of a yield.